At the heart of it all ... the "CS2000" from Cirrus Logic

A "clocking IC" that is a clock generator and clock multiplier/jitter-reduced clock frequency synthesizer (clean up)

The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid ana-log-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an exter-nal noisy synchronization clock at frequencies as low as 50 Hz. The CS2100-CP supports both I²C and SPI for full software control

Let's Study the Digi-Key Parts Page ...

Fractional-N Synthesizer Basics

(http://www.holmea.demon.co.uk/FracN/Synth.htm)

The minimum step size of an integer-N synthesizer equals the reference frequency (fREF). Fractional-N synthesizers break this coupling; the steps can be very small indeed. Designers are free to increase comparison frequency and widen loop bandwidth - lock time is thus reduced; reference spurs and microphonics are eliminated. Fractional spurs, however, are a new hazard.

Fractional-N synthesizers work by periodically changing the division ratio from N to N+1 and back such that the average is N + F/M where 0≤F<M; N,F and M are integers. For example, if N is 5 for 99 cycles and 6 for one cycle, 5.01 is the average division ratio. An attached frequency counter would read 5.01 times fREF.

Unfortunately, there's a catch: switching the division ratio seriously disturbs the PLL resulting in a sawtooth-like waveform on the VCO control line and severe FM sidebands on the output. Fortunately, the disturbance is predictable - and various means have been devised to cancel it.

Fractional-N synthesizers first appeared in the late 1960s and early 1970s. The earliest compensation schemes applied analogue correction to the VCO control line. A notable design was the synthesizer by Nigel King for the RACAL RA1792 communications receiver. A breakthrough came in 1984 when John Wells of Marconi Instruments invented an entirely digital scheme based on the principle of noise shaping.

Noise shaping concentrates the quantisation noise produced at the PFD output into the higher frequencies where it is removed by the low-pass filter. The loop structure is shown opposite.

The divider is controlled by a form of sigma delta modulator known as a MASH. The division ratio N+ΔN is not confined to N and N+1, it depends on the number of stages (order) of the MASH.

MASH output, ΔN, is a pseudo-random sequence. The VCO frequency is governed by the long-term mean of ΔN which is exactly F/M. Please visit my MASH Theory Page for a mathematical treatment.

The MASH structure is a series of first-order sigma delta modulators, each fed by the quantisation error of the previous stage.ΣΔ modulators are widely used in A/D and D/A conversion, to achieve high resolution from fast low resolution (e.g. 1-bit) converters by oversampling. The ΣΔ modulator is followed by a low pass filter. Conveniently, in A/D applications, it's a digital filter. A very readable retrospective on ΣΔ modulators can be found in chapter 3 of Ushaw^[2].

Switching Signals

The AS169 GAS PHEMT GaAs IC SPDT Switch 300 kHz–2.5 GHz

- General purpose medium-power switch

- P1 db 30 dBm typical at 3V

- IP3 52 dBm typical

- Low insertion loss (0.3 dB @ 900 MHz)

- Low DC power consumption

So let's look next at the Mouser spec summary ...

Conceptual Block Diagram

Description

- clock generator chip uses fractional N dividers and digital PLL

- quartz crystal gives good accurate and stability

- fractional N divider gives good frequency resolution

- PLL cleans up phase noise

- clock chip spec indicates 6 to 75 MHz output ... can use tricks to boost freq

- RF output is a square wave, not the usual sine wave

    > contains harmonics of the fundamental frequency

    > for a perfect square wave even harmonics (2, 4, 6, 8...) are negligible

    > odd harmonic attenuation:

        3^rd harmonic -9.7 dB

        5^th harmonic -13.8 dB

        7^th harmonic -16.9 dB

        9^th harmonic -18.1 dB
 

- Front end selectivity of most receivers will remove harmonics

- Plus many ham bands are even harmonics of lower ones

- Possible leakage may affect calibration at higher frequencies

- Coupling across resistive attenuators is frequency dependant

- Leakage around solid state switches increases with frequency

- Clock generator may radiate thru non-shielded case

- Internal battery use lessens leakage through power leads

Prototype

Signal Source Uses

- General frequency spotting

- Rough frequency calibration

- RF level calibration (or ballparking) in receivers

- S-Meter calibration

- RF probe calibration

- Rough calibration of RF Meters

- Rough scope calibrations: o'scope, spectrum analyzers,

- Debugging new radio designs

- Troubleshooting problems in existing radios

- Code Practice Oscillators

- Signal source for antenna tuning & diagnosis

- Fox hunts

- Beacons

- Local oscillators / QRPpppp transmitters

Signal Sources on the Market

1. Fractional-N Sythesizers, RF Design ... http://mobiledevdesign.com/images/archive/1100Appel34.pdf

2. Fractional-N Synthesis, IFR App Note ... http://www.spg-tm.com/ats/products/prodfiles/appnotes/446/890.pdf

3. Basics of Dual Fractional-N Synthesizers/PLLs,SkyWorks, http://www.digikey.com/Web%20Export/Supplier%20Content/SkyworksSolutions_863/PDF/Skyworks_WP_101463B.pdf?redirected=1

4. XG3 Signal Source, Elecraft, http://www.elecraft.com/XG3/xg3.htm   (See an overview video at http://www.youtube.com/watch?feature=player_embedded&v=vhrW4UkJ2_U)

5.    Frequency spectrum of a square wave: <http://www.informit.com/articles/article.aspx?p=1374896&seqNum=7>

6.    Clock chip: <http://www.cirrus.com/en/pubs/proDatasheet/CS2000-CP_F2.pdf>

7.    Solid state switches: <http://www.skyworksinc.com/uploads/documents/200105E.pdf>

8.    Fractional/Integer-N PLL Basics, TI Technical Brief SWRA029: http://www.ti.com/lit/an/swra029/swra029.pdf

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